Project to create an ATX 80286 mainboard based on the IBM 5170

[rodney]

For everyone following my project, I have really great news!

I have done some testing with the 5170 reference mainboard since I wanted to exclude larger system areas from having issues. So I have removed the DRAMs, memory transceivers and a few other ICs from the refresh generator, created the memory card header from various points on the 5170, and I have done some testing. The result was that the 5170 worked perfectly with the memory card, showing the whole 2MB of soldered SRAMs on the board. I have run the 5170 for a few hours without a single crash. The 5170 didn't show any screen update issues, so I was certain that the memory card had no issues at all.

Next I proceeded to completely disable all REFRESH logic, and removed some ICs to more closely match the state of the 5170 to my prototype. All the software I ran on the 5170 worked fine.

I also switched off the system timer signal just to see the impact on the system, but this was not able produce any screen issues. At the most I found the system just waiting until I re-enabled the system timer and it continued as normal.

After that I decided to take some scope measurement screenshots of the CPU cycle control signals on the 5170, since the cycle control was working perfectly there. The 286 cycle control logic and byte conversion logic is in my view the most timing sensitive area of the whole AT system. So I decided to first look at the CPU cycle control since this also propagates into the byte conversion timings.

I powered up the prototype and started to probe the cycle control signals, where the first thing I noticed was that the /ARDY pulses looked rather short in the length of their positive phases. So the "not ready" states were looking a little on the short side compared to the 5170 scope images. I have a very cheap scope however thankfully I was able to find this from the measurements shown.

So after doing a few tests to improve the timing of /ARDY, I could immediately see differences in the screen update issues when I looked at the MR BIOS screen. I did a few tests to extend the /ARDY pulse duration by shifting it through an additional flipflop, finally, using the the inverted CPU clock and applying IOCH_RDY to the second flipflop as well, I got the system working without any screen issues! The problem which I have been looking at for a few weeks is now completely solved!

Apparently the problem was in the /ARDY operation of the System Controller CPLD where the timing at which the signal was switching was too fast for the 82284 and the 286 CPU. After fixing this problem I found a much more stable operation of the whole system. No more beeps from MR BIOS so far and the RTC is keeping the CMOS settings well, which results in a normal power on and proceeding to the boot screen right away.

So all the issues I have found so far were all able to be solved inside the CPLDs, which can really show their prototype design value! I don't need to change anything in the PCB layout.

I have seen a huge improvement in the stability of the AT system since I fixed the cycle timing. Now it really looks like a fully stable AT PC. I will do further testing since I still need to test the onboard RTL8019AS LAN connection and SCSI adapter, I need to order some NCR 53C400 chips for that. Also I still need to program a serial EEPROM for the LAN chip configuration using a ISA adapter card and the configuration program. I don't have any supply of those EEPROMs so I will need to use the one I do have here. The DS12885 RTC is now working just as reliably as the MC146818 by changing two jumpers, so I am happy about that. The RTC is powered by the 5V standby power from the ATX PSU so it will not use any battery current as long as the power cable is plugged in and the back power switch is turned on on the PSU.

The prototype PCB is working really well above what I expected because I always considered that I might need to design and manufacture at least another revision of the PCB, however At the moment I don't see any reason to need to do this.

I will update the Github information with all the final CPLD JEDEC programming files and everything needed to build this AT design.

So now I will also start enjoying to test the system even more and play some games etc on it!

Kind regards,

Rodney

 

[rodney]

My understanding is that the biggest pain point for moving up to an 8086 or 80286 design is having to intercept accesses from the CPU to 8-bit peripherals and split them up appropriately

Hi Makefile,

You were the first person to reply my post when I started this thread for the project.
And after reading your message again, you were absolutely spot-on in your estimation of the project, very insightful indeed!

I can report you that the prototype is now working well, and I indeed used CPLD technology to replace the PALs and PROMs originally used on the 5170.
It took me a whole year of hard work to get to a stable AT system and I had some really helpful assistance and inspiration on this forum.

At it's core the system includes the original technology as developed by Don Estridge of IBM.
It's a great experience to be able to test an AT recreation based on his amazing design!

The project is fully available on Github for anyone who is interested.

Kind regards,

Rodney

 

[Hak Foo]

This is an incredible project. You've basically recreated an unobtanium class of hardware-- the "commodity 286" chipset-- in a way that feels both "historically appropriate" and "actually buildable with parts you can find today". This is in some ways a bigger deal than just systematically copying what the 5170 did.

Somehow, this feels more authentic than just wiring up a modern MCU to do all the bus brokerage. I wonder if the firms known for 286 chipsets like VLSI and Headland used early FPGAs/CPLDs in a similar way in the 80s to prototype their products.

 

[mogwaay]

Hi Makefile,

You were the first person to reply my post when I started this thread for the project.
And after reading your message again, you were absolutely spot-on in your estimation of the project, very insightful indeed!

I can report you that the prototype is now working well, and I indeed used CPLD technology to replace the PALs and PROMs originally used on the 5170.
It took me a whole year of hard work to get to a stable AT system and I had some really helpful assistance and inspiration on this forum.

At it's core the system includes the original technology as developed by Don Estridge of IBM.
It's a great experience to be able to test an AT recreation based on his amazing design!

The project is fully available on Github for anyone who is interested.

Kind regards,

Rodney

This is amazing! Having an open source 286 custom chip set that can be synthesized using commodity CPLDs is so brilliant! Such a cool project and I think many folks (incline when I find time and money) would love to have a go at building. Bravo!

Very impressed (and relieved for your bank balance!) that you managed it in a single board revision!

 

[rodney]

I wonder if the firms known for 286 chipsets like VLSI and Headland used early FPGAs/CPLDs in a similar way in the 80s to prototype their products.

Hi Hak Foo,

Thanks for your reply, I appreciate it very much!

I fought a hard battle to reach this design, because there were a lot of elements to the system which needed to be mastered.

I knew that CPLDs, just like PALs, can offer much faster timing than loose TTL logic.
Intel CPUs are more sensitive to timing so this becomes increasingly important when upgrading the CPU.
CPLDs offer better technology however it's also requiring more work and testing to get the timing right.
This project has taught me a lot about shifting signals through flipflops.
And I have been able to experiment a lot using the CPLDs.
The most sensitive component is of course the Intel CPU itself.
I now know the symptoms when the timing is off, which will be a useful experience for the future I am sure.

But it also is really rewarding to see the system work much faster and more solid when the 286 CPU is in its element!
The CPLDs are able to be much more accurate than when using TTL for decoding and shifting signals.
After I made the final changes, I measured the /ARDY signal and it just looks really solid and good.
That's the advantage of syncing signals to some phase or synchronized multiple of the clock.
The whole PC has become super solid now and it's a delight to use it.

actually buildable with parts you can find today

Exactly, this has always been my concern, that the design must be reproducible for sharing and preserving the technology.
So I chose the path which is more difficult and more work after finishing the PCB design because it's partially unknown territory since nothing has ever been shared by the chipset brands.
All we have left now is their datasheets and declining numbers of surviving chips available, so I avoid using any commercial chipsets for anything.

I will look more into other chip technologies which can support this in future designs.
And I will be creating and sharing VHDL or Verilog code versions of the CPLD components.
I will do what I can to make everything about this system documented and available for the future.

I agree, I also don't like using modern MCUs in a legacy system in the ways you described. I made a small exception to include Adam's USB to serial interface using the RP2040, but this is only on the other side of the UART serial port and not involved in system or bus control. This project by Limeprogramming is such a big "keeper" that I can not resist including it on any future PC design! Seen from the 286 CPU it functions exactly like a serial mouse from the same time period which is also a very good functional match to the whole system. It's a joy to play legacy games with a good mouse. I will look into testing even smaller RP2040 PCBs for adapting a USB mouse in the future.

I know there is work being done to recompile Doom to operate on older systems, as I understand that besides CPU power it especially needs a lot of memory, which was actually the motive for me to enable the full memory range of the 286 on the memory card layout just to see how it could perform. Poorly, of course, but it's still fun to look into this if it's able to run.

It's great to hear from you Hak Foo, and thank you for your inspiring words!

Kind regards,

Rodney

 

[rodney]

Having an open source 286 custom chip set that can be synthesized using commodity CPLDs

Hi mogwaay,

Thanks for celebrating the happy news with me! I appreciate that!

Yesterday after I got the breakthrough late in the night after doing a lot more testing on the 5170, I suddenly got an inspiration to try a few things on the prototype.
I had done similar modifications and tests in the past two weeks, so I am very happy that I decided to continue more on this path of timing and synchronization experimentation.

And the feeling to see the key modifications clear up all the issues suddenly after one of countless RESETs is indescribable, I just suddenly felt so energized by the experience!
The PC now really feels like a whole new AT system compared to before, which is thanks to the successful timing realized with the CPLDs.
And I really appreciate and I am grateful for having the magic of Don Estridge's design preserved, alive and functioning really well in the core of the project!

Indeed, this project has cost me in the past year, especially buying 4 reference mainboards, a new desoldering iron and of course manufacturing the PCBs, and in time and loss of sleep over the project.
Really, those sessions working through the night are sometimes essential because you can't just quit a train of thought, you have to try to ride it through to get anywhere!

It's funny that the 5170 mainboard which I found by coincidence actually cost me the least of all of them, and works the best, so a big luck and boost for the project!
Before I thought that the AT mainboards from that era were mostly similar as long as they are not defective, but now I also know the nuances between some of them.
The 5170 is really the winner, I have found this by doing extensive testing!

I have looked at other PCB factories, but so far, unless I find out differently in the future, JLCPCB is the champion of balancing quality with price!

The PCB can withstand desoldering work, which it shouldn't have to but I have a big shortage on IC sockets so I have soldered in the parts directly at first, and only desoldered them for placing sockets if this was really necessary for the work. I recycled a lot of parts from the other 3 mainboards which didn't work well, including ISA slot connectors etc.
So in this way and other ways I was able to save costs as much as I could. I learned to use a cheap paint stripping gun with careful control to serve as a hot air soldering iron, which absolutely made all the difference after desoldering parts. This model had two settings so I was able to use the lower setting succesfully, though if you are not careful and if not handled exactly right, it will definitely be very capable to burn and desintegrate a PCB. I also used other defective or useless PCBs to salvage GAL chips, IC sockets, etc.

Now that everything is working which I have tested on the system, if I see any ways to save costs, I will write about it here in the thread along with all other information.
After I knew that this first revision mainboard will suffice for the project, I also felt relieved and it's a lucky and welcome fact!

Yesterday I plugged in and tested all the VGA cards I have here, they all work perfectly.
I still can recommend the Video Seven Headland VGA 16E card, during my debugging work this card worked the best of all cards I have been able to test.
It seems this VGA design is really good and accurate which was also a great help to the project.

Kind regards,

Rodney

 

[rodney]

I am still testing some remaining stuff, and I made an update of the System Controller CPLD where I am now testing the DMA clocked at 4,77Mhz.
Which is what I originally intended but temporarily changed to 4Mhz for testing reasons.

So far it's looking fine, I am able to format and write floppy disks, boot from them and I tested some games with audio samples.
So unless I find any issue, I will keep this higher DMA speed which can benefit action games which load sound data during gameplay for example.

Today I will test with the UART and RP2040 for enabling the USB mouse port on the mainboard.
This needs a small plug in PCB for the RP2040, I could design a PCB but it's so simple that any simple solder job using a few wires also will work just as well.
The headers on the mainboard contain all the signals and I will document this in full detail.

If I have time I will probably also solder and test the RTL8019AS LAN chip.
I need to program an EEPROM with the correct settings, but I can also test the existing version.
The 16 bit enable will work automatically so I doubt this needs any software changes.

I will try to source some 53C400 SCSI chips but this is so basic and such a well made chip by NCR, I don't think it needs anything except soldering in the parts and loading the drivers.
The SCSI is 8 bit so the system will do conversions, but I am sure it still will reach reasonable speeds for general purpose such as making some backups, reading a CDROM or exchanging files.
That is what the chip was included for and in my opinion really suitable for.
The bonus is that it's PLCC so it can be inserted into a through-hole socket.

Kind regards,

Rodney